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www.fairchildsemi.com ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 6/1/10 AN-8021 building variable output vo ltage boost pfc converters with the fan9612 interleaved bcm pfc controller abstract the output voltage of a boost pfc converter has to be set above the highest input voltage of the source in order to maintain boost operation and be able to shape the input current waveform of the power supply. for universal input voltage designs, the appropriate output voltage selection is about 400v dc . in many applications, it might be desirable to adjust the output voltage according to the input ac rms voltage level, the output power of the converter, or both. the fan9612 interleaved bcm pfc controller is particularly suited to implement such designs because the non-inverting input of the voltage error amplifier is easily accessible to adjust the converter?s output voltage. this applic ation note gives details about how to make the boost output voltage the functi on of the output power of the converter. circu its with variable level of sophistications are shown and explained. furthermore, it describes the design and implementation of the boost follower concept where the output voltage becomes th e function of the input ac rms voltage level. why adjust v out ? the output voltage of the power factor correctors (pfc) front-end is defined by many requirements and operating parameters of the power supply. pfcs draw power from the input source following a sine square function while their output is loaded with a practica lly constant load, as depicted in figure 1. figure 1. instantaneous input and output power of a pfc front-end therefore, energy storage must take place in the power factor corrector on the line frequency basis. this energy storage is most efficient at high output voltage, such as 400v dc . on the other hand, the switching losses of the boost converter and the downstream isolated dc-dc converter are both proportional to the output voltage of the pfc. higher output voltage increases switching losses, which is most noticeable in the light-load efficiency of the power supplies. consequently, the output voltage should be kept the minimum allowed by the fundamental requirements to maintain feasible operating conditions for the boost converter. these opposing requirements of: ? keeping the output voltage above the highest input voltage level; ? using the highest possible voltage to improve volumetric efficiency of energy storage; and ? lowering switching losses by selecting the lowest possible output voltage; might lead to the implementation of a system where the boost output voltage is optimized for the momentary input voltage and load conditions. these solutions are the focus of this application note. how to adjust v out ? the fan9612 is unique among the pfc controllers because of the full accessibility of its error amplifier. in addition to the inverting input (fb) and the output of the error amplifier (comp), which must be available for output voltage sensing and compensation, the non-inverting input (ss) is also accessible, as shown in figure 2. the non-inverting input of the error amplifier is connected to a voltage reference (v ss ) generated across the soft-start capacitor (c ss ). the feedback divider (r fb1 and r fb2 ) is connected to the inverting input of the error amplifier through the fb pin. the reference voltage, together with the feedback resistors, sets the desired output voltage according to the expression depicted in figure 2.
AN-8021 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 6/1/10 2 figure 2. external connections of the error amplifier the fan9612 allows the output voltage of the converter to be adjusted either by modifying the feedback network or by changing the reference voltage. changing the feedback divider gain affects the closed-loop gain of the converter; thus, it can cause stability problems or set unacceptable limitations on the control loop bandwidth. conversely, changing the reference of the error amplifier has no effect on the loop gain and utilizes the same mechanism used during the closed-loop soft-start of the converter. furthermore, this approach does not affect the over-voltage protection levels of the converter. while either method can vary the output voltage of the converter, changing the reference of the error amplifier is a better solution. when to lower v out and how low to adjust? the output voltage of the power factor corrector is carefully selected to meet the design requirements. nevertheless, there are certain combinations of operating conditions that would allow adjusting the converter?s output voltage lower to benefit from reduced switching losses. for instance, when the input voltage is not at its maximum value, the boost output voltage could be reduced; but the effects of the lower output voltage on the system must be carefully considered. one of the factors that must be taken into account is the required hold-up time, a specification which defines that the output voltage must stay above a minimum level for a predetermined length of time in case the input voltage suddenly disappears. this minimum voltage is a function of the operating input voltage range of the downstream isolated dc-dc power supply. this system-level specification primarily influences the value of the energy storage capacitor at the output of the pfc, which also serves as the input capacitance for the downstream converter. usually, the capacitance is calculated for the worst-case condition when the system delivers full output power. it can be estimated as: 2 min out, 2 nom out, up hold max out, out v v t p 2 c ? ? ? = (1) when the output voltage is kept constant, the resulting hold- up time is longer than required at lighter load conditions. for a given power stage design where the capacitor value is fixed, it is possible to lower the output voltage of the power factor corrector under light-load conditions without violating the hold-up time specification: () 2 min out, 2 nom out, norm out, 2 min out, norm out, out v v p v ) (p v ? ? + = (2) where max out, out norm out, p p p = (3) is the normalized output power of the pfc converter. assuming 400v dc for the nominal output voltage and 340v dc as the minimum at the end of the hold-up time, figure 3 shows the solution for the minimum boost output voltage as a function of the normalized output power to maintain the hold-up time requirement for the system. p out (normalized) v out 340v 360v 380v 400v 01 figure 3. boost output voltage as a function of normalized load conditions (t hold up =constant) it is important to notice that, despite the square root function in the exact mathematical solution, the graph shows a nearly linear relationship between the normalized output power and the output voltage of the converter. in fact, the output voltage can be accurately estimated by: () min out, nom out, norm out, min out, norm out, lin out, v v p v ) (p v ? ? + = (4) the error between the linearly approximated output voltage in equation (4) and the exact solution given in equation (2) remains well below 1% under all load conditions, as illustrated in figure 4.
AN-8021 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 6/1/10 3 p out (normalized) 01 0 0.1 0.2 0.3 0.4 error [%] figure 4. percentage error between the output voltages given by equations (2) and (4) the important conclusion of the presented analysis is that the output voltage can be a linear function of the output power. this finding eases the circuit implementation to vary the output voltage according to the load conditions. the fan9612 controller makes this task even easier since its control technique utilizes input voltage feed-forward. the output of its error amplifier is directly proportional to the output power of the supply. another consequence of lowering the boost power factor corrector?s output voltage as a function of the output power might become apparent during rapid load increase. due to the doubled line frequency ripple across the output capacitor, pfc converters employ an extremely slow voltage regulation loop. typical voltage loop bandwidth is around 10hz in pfc applicatio ns. in contrast, the control loop bandwidth of the downstream dc-dc converter is approximately two orders of magnitude higher, typically a few khz. as a result, it is unavoidable that the boost output voltage sags temporarily in response to quickly increasing output power demand. if the output voltage of the pfc converter was low due to the preceding light-load operation, the output voltage transient window is severely limited before the input under-voltage protection threshold of the downstream converter is activated. therefore, the adjustment range of the boost output voltage has to be carefully selected and the light-load operating voltage must be kept sufficiently above the minimum input voltage (v out,min ) of the dc-dc converter to accommodate output voltage variations during load transients. v out 100v 200v 300v 400v v in,pk v in,rms 265v 65v figure 5. output voltage set point of the boost follower in some instances, when the downstream dc-dc converter works acceptably over a wide input voltage range, it could be possible to adjust the boost output voltage as a function of the input ac rms voltage. this implementation is called the boost follower, where the pfc output voltage is proportional to the rms value of the ac input voltage. figure 5 shows a potential approach where the boost output voltage is set above the peak input voltage level by a fixed offset. the example highlights the wide pfc output voltage variation of this technique, which can present a challenge designing the downstream converter. furthermore, an almost 3:1 output voltage variation between 400v dc and approximately 140v dc , as shown in figure 5, results in energy storage variation of 9:1 at the output of the pfc converter. at the low end of the output voltage range, the doubled line frequency ripple would increase significantly further, escalating the required input voltage range of the dc-dc converter connected to the pfc output. hold-up time capability would also be significantly impaired at low line, unless the output capacitance is significantly increased. note that the higher output capacitance value would have a positive effect on the ripple amplitude as well. furthermore, the previously outlined hold-up time and transient considerations are equally applicable in the boost follower applications. table 1. comparison of output voltage adjustment strategies boost follower load dependent output v out function v out (v in,rms ) v out (p out ) v out range wide narrow output capacitance large, based on output ripple small, based on hold-up time hold-up time strong function of v in,rms per specification transient response strong function of v in,rms weak function of p out dc-dc input range wide narrow
AN-8021 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 6/1/10 4 the difference between the boost follower implementation and adjusting the output volta ge according to the load is summarized in table 1. although it was not directly emphasized, the instantaneous peak input voltage of the pfc stage and the minimum operating input voltage of the downstream converter always limit the boost output voltage adjustment range. simple v out adjust by p out as mentioned earlier, the error amplifier output of the fan9612 bcm pfc controller is proportional to the output power of the power stage it controls. the pwm ramp offset in the fan9612 is approximately 0.2v (v ramp,offset ). when the error amplifier output is below this voltage, no pwm output pulse is generated. therefore, v comp =0.2v corresponds to zero output power. the converter delivers its maximum output power at approximately v comp =4.5v. accordingly, the relationship between the error amplifier?s output voltage and the converter?s output power is given as: ( ) norm out, comp offset ramp, norm out, comp p v v p v ? + = (5) where v comp is the control range of the error amplifier (4.3v). utilizing the proportionality between p out and v comp , the output voltage can be easily adjusted. figure 6 shows one of the simplest implementations that can adjust the boost output voltage to a user-defined minimum level under light- load conditions. figure 6. output voltage adjustment by output power the circuit consists of the r1, r2 divider, which sets the lowest output voltage corresponding to no-load conditions. in addition, an ?ideal diode? (see additional implementation details toward the end of this application note) formed by the operational amplifier u1 and the diode, d1, connected to its output is us ed to adjust the reference of the error amplifier across th e soft-start capacitor, c ss . the design procedure starts by choosing the desired output voltage at zero load, v out,0 and selecting one of the resistor values, r2 for example. r1 can be found by: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 1 v v v 3v v 5v r2 r1 offset ramp, nom out, out,0 offset ramp, (6) where v out,nom is the nominal output voltage at full load and v ramp,offset is the pwm ramp offset found in the fan9612 datasheet. while the value of r2 can be selected by the designer, it is important to draw attention to the fact that the r1, r2 divider introduces a dc current into the output of the g m - type error amplifier of the fan9612. this dc current component must be kept very low to avoid introducing a large voltage regulation error. typical current levels should be in the a range, which necessitates that the resistance of r2 is chosen in the 300k ? to 500k ? range. the worst-case output voltage regulation error occurs at no load and can be estimated as: fb2 fb2 fb1 m offset ramp, offset out, r r r g r2 r1 v 5v v + ? ? + ? = (7) where g m and v ramp,offset are datasheet parameters; r fb1 and r fb2 forms the feedback divider according to figure 2; and r1, r2 resistors are part of the schematic introduced in figure 6. the performance of the solutions is illustrated in figure 7. p out (normalized) 01 v out 300v 350v 400v 450v 1v 2v 3v 4v 5v v ss v comp figure 7. v ss , v comp , and v out as a function of normalized output power as figure 7 shows, the output voltage of the converter is gradually reduced when the load drops below 20% of the maximum output power. v comp and v ss are also shown for completeness. while this circuit is very simple and requires only a few external components, the designer can only choose the minimum output voltage level. this circuit does not allow selecting the power level where the output voltage starts decreasing.
AN-8021 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 6/1/10 5 flexible v out adjust by p out adding two additional resistors, r3 and r4, to the circuit shown in figure 6 offers additional flexibility to consciously pick the output power level where the converter?s output voltage adjustment commences. 3 r1 r2 error amplifier fan9612 8 7 6 comp ss fb c ss 5vb r3 r4 v adj u1 d1 figure 8. flexible output voltage adjustment by output power to start the design, two application parameters need to be established and two resistor values to be selected. the output voltage at zero load is v out,0 , the output power level where the output voltage adjustment begins is p adj , and they can be part of the power supply specification. in addition, one resistor of each divider can be selected by the designer; for instance, r2 and r4. notice that the r1, r2 divider current is provided by the r3, r4 divider; therefore, the current flowing through r3 and r4 must be at least two orders of magnitude larger to avoid interaction between the two networks. fortunately that requirement is aligned perfectly by the restriction to keep the r1, r2 divider current at a low value to avoid output voltage regulation error. the step by step design procedure is outlined in equations (8) through (12). the final value of the error amplifier?s reference voltage, v ss,0 , corresponding to the output voltage at no load is: nom out, out,0 ss,0 v v 3v v ? = (8) where v out,nom is the nominal output voltage at full load and 3v is the reference voltage of the error amplifier. the error amplifier?s output at the onset of output voltage adjustment can also be determined by: () max out, adj comp offset ramp, adj comp p p v v p v ? + = (9) the appropriate value of v adj , the voltage set by the r3, r4 divider according to the schematic shown in figure 8, can be calculated as: ( ) () () offset ramp, adj comp ss,0 offset ramp, adj comp ss,0 adj v 3v p v v v 3v p v v v + ? + ? ? ? = (10) after selecting r4, typically in the 5 to 10k ? range, r3 can be defined to set v adj to the calculated voltage based on: ? ? ? ? ? ? ? ? ? ? = 1 v 5v r4 r3 adj (11) to ensure that the current of r1 and r2 divider does not influence the voltage established by r3 and r4 (v adj ), select r2=100r4 . the value of r1 is then found by: ? ? ? ? ? ? ? ? ? ? ? ? = 1 v v v v r2 r1 offset ramp, ss,0 offset ramp, adj (12) the final circuit performance is demonstrated in figure 9. p out (normalized) 01 v out 300v 350v 400v 450v 1v 2v 3v 4v 5v v ss v comp figure 9. v ss , v comp , and v out as a function of normalized output power in summary, the circuit shown in figure 8 accommodates user programmable output voltage adjustment of the boost pfc converter as a function of the output power. the resistive divider comprised by r1 and r2 sets the lowest output voltage level corresponding to no-load condition and the r3, r4 divider determines the power level where the output voltage starts decreasing. the example solution in figure 9 is designed to reduce v out from its nominal 400v to 340v linearly, while the converter?s output power decreases from 70% of its maximum value to zero, respectively. universal v out adjust by p out one potential shortcoming of these solutions is that the programmed output voltage of the boost converter might become lower than the peak of the input voltage. this could occur when high line and low power conditions occur together. at that point, depending on the chosen v out,0 level, the boost converter might become a peak rectifier and power factor correction would be lost. to remedy the situation, the input voltage has to be monitored and the information used to limit how low the output voltage can be adjusted.
AN-8021 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 6/1/10 6 3 r1 r2 error amplifier fan9612 8 7 6 comp ss fb c ss 5vb r3 r4 v adj r6 r7 c1 c2 r5 r in2 (r in1 -r5) 10 vin v in (t) v lim d1 u1 u2 d2 k in v in (t) figure 10. universal output voltage adjustment by output power with input voltage override figure 10 introduces a prospective solution. the circuit builds on the previously analyzed schematics, shown in figure 6 and figure 8, adding an averaging filter to monitor the input ac rms voltage level and a suitable interface to use the measurement result to limit the v out adjustment range during high line operation. the component selection for r1 through r4 resistors follows the same procedure outlined in the previous section. the input voltage is measured by the averaging filter comprised of r6, c1, r7, and c2. the voltage across c2 is utilized to limit how low the output voltage can be adjusted. the interface between the input voltage measurement and the output voltage adjustment circuit is provided by another operational amplifier, u2, and a diode, d2. the effect of u2 and d2 is an ?ideal, source-only diode? that can only raise the voltage determined by r1 and r2. the c2 voltage overrides the control voltage generated by the r1, r2 divider at the non-inverting input of u1. note that any voltage less than the 3v internal reference voltage of the fan9612 at the non-inverting input of u1 is forced across the soft-start capacitor c ss and ultimately determines the output voltage. the main motivation for introducing the input voltage information to the output voltage adjustment circuit is to ensure that a minimum voltage is always present to ramp the boost inductor current down to zero. that minimum voltage is basically the difference between the peak of the ac input voltage waveform and the output voltage. that is why, when the input voltage rises, it might be necessary to override the output voltage set point as defined by the output power. before the circuit parameters can be calculated, this minimum reverse voltage across the boost inductor (v l,min ) must be chosen by the designer. this voltage, v l,min , defines the input voltage scaling factor, k in , according to: () min l, out,0 nom out, out,0 in v v v v 2 3v k ? ? ? ? = (13) where 3v is the nominal value of the error amplifier reference, v out,nom is the nominal output voltage before any adjustment applied, and v out,0 is the desired lowest output voltage at no load; assuming the ac input voltage is not limiting the adjustment range. as indicated in figure 10, sensing the input voltage for the limiter can be combined with the input voltage divider already present in the circuit, providing the scaled down input voltage information for the vin pin. the values of r in1 and r in2 are based on the brownout specification of the power supply. the design procedures for those components are part of the fan9612 quick setup guide included in the datasheet and can also be found in the application note an-6086 titled ?design consideration for interleaved boundary conduction mode pfc using fan9612.? usually, the vin pin requires a lower voltage than the output voltage limiter. therefore, r in1 has to be split into two resistors, r5 and the remainder of the originally calculated r in1 resistance to provide the appropriate scaling. assuming that the design retains the original value of r in1 and r in2 , r5 can be calculated as: ( ) in2 in2 in1 in r r r k r5 ? + ? = (14) since the input voltage waveform, v in (t) follows a rectified sinusoidal shape, it can not be directly used to limit the output voltage. its average value, which is provided by the averaging filter comprised of r6, c1, r7, and c2; must be
AN-8021 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 6/1/10 7 used. these components implement a two-stage low-pass filter. the filter design is based on the lowest frequency of the input ac source, f line,min . the filter?s recommended corner frequency can be set according to: min line, p f 0.15 f ? = (15) the component values are defined by: c1 f 2 1 r7 r6 c2 c1 p ? ? ? = = = (16) where c1 should be selected to ensure that the resistor values (r6 and r7) are in the 500k ? range. it is necessary that the filter does not load the input voltage divider; thus r6 and r7 must be high impedances. since the filter network does not utilize any resistor connected to gnd, it does not cause any measurement error in the functions based on the accurate scaling of the input voltage for the vin pin. assuming that the minimum line frequency is 47hz, the recommended component values are c1=c2=47nf and r6=r7=470k ? . the combined effect of input voltage and output power variations yields the output characteristic shown in figure 11. figure 11. v ss , v out , and v in,peak as a function of the input rms voltage as figure 11 illustrates, the output voltage of the converter is adjusted according to the outp ut load as long as the peak of the input ac voltage waveform stays at least 40v below the desired output voltage. at high ac line conditions, the output voltage is a function of the combination of the load and the input voltage, keeping the output approximately 40v above the peak of the input waveform. two-level boost output voltage implementation it is conceivable that the boost output voltage is not adjusted continuously as a function of the load or the input voltage, rather switched between two discrete set points as a function of the input ac source, as illustrated in figure 12. v out,h v out,l v in,sw 265v rms 65v rms figure 12. two-level boos t output characteristic this solution could be considered when the boost output voltage would be regulated at the nominal level, v out,h , when the pfc is powered by a nominal 230v ac source. but it would be regulated at a different lower voltage, v out,l , when the source is a 120v ac line. while this concept sounds relatively simple, implementing it might be difficult due to incompatibility of the various voltage levels. there are two fundamentally different approaches to this problem. for instance, the designer can define the input ac rms voltage level, v in,sw , when the switch over takes place between the two output voltages. in this case, the minimum output voltage, v out,l is somewhat limited. it must sufficiently above the peak of the input ac waveform. min l, sw in, min l, out, v v 2 v + ? = (17) where v l,min is minimum reverse voltage across the boost inductor as defined earlier. according to equation (17), if the switch over should be at 150v rms and the minimum inductor reverse voltage is 40v, the lower regulation level can not be below approximately 250v dc. in another scenario, v out,l is chosen and the input rms voltage level where the switch over occurs is somewhat defined. 2 v v v min l, l out, sw in, ? = (18) for example, v out,l =220v would force the designer to switch to the higher output voltage level at 127v rms input to preserve 40v minimum reverse voltage across the boost inductor. this voltage level is still considered within the normal tolerance range for a 120v ac source in the us and some asian countries. as can be seen, selecting the right voltage levels for a two-level boost converter can be challenging. it is desirable that the switch over between the two output voltage levels should occur between 140v rms and 198v rms . these voltages signify the upper limit of the 127v ac and the lower limit of the 220v ac sources, respectively. in view of that, the nominal v out,l voltage should be kept above 250v dc and it would be desirable to set it around 300v.
AN-8021 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 6/1/10 8 a few other problems, which should be seriously considered when the output levels are selected, are the amplitude of the line frequency ripple voltage across the converter?s output capacitor and hold-up time requirements. the issue is that energy stored in the capacitor is proportional to the square of the output voltage. assume that the output capacitor is calculated for 400v output and +/-20v (i.e. +/-5%) line frequency ripple at full load. at 300v output, the ripple would grow to +/-35v (or +/-12%) and, at 200v, it would reach +/-80v (equal to +/-40%). generally, the lower the output voltage set point is, especially v out,l , the output capacitance of the converter must be significantly over designed to keep the line frequency ripple under control. similarly, meeting the hold-up time requirement at a drastically lowered output voltage level imposes a severe penalty in output capacitance. once the suitable output voltages are established, the circuit diagram shown in figure 13 can be used to implement a two-level boost power factor corrector. the circuit implementation includes two sections, r8, r9 and the ?ideal, sink-only diode? comprised of u1 and d1 is used to establish the v out,l voltage level. in the other section of the circuit, u2 is configured as a comparator, where its threshold for the output voltage switchover is determined by r11 and r12. the transistor q1 and r13 provides hysteresis for the comparator. the output of the comparator, together with d2, r10 current limiting resistor, and c3 filter capacitor; is used to override the voltage presented at the non-inverting input of u1. once the peak input voltage exceeds the desired value corresponding to v in,sw , the comparator output goes high and peak charges c3 filter capacitor to approximately a diode forward voltage drop less than u2?s 5v bias voltage. at that point, d1 becomes reverse biased and c ss is charged to its nominal 3v level, which corresponds to the nominal output voltage of the converter, v out,h . the wide hysteresis established by r13 and q1 ensures that the output of u2 remains high for approximately one quarter of a line period to be able to charge c3 to the final voltage level at the first trigger event of the comparator. the design procedure of this circuit starts by setting v out,l . the lower output voltage level is established by r8 and r9 and these resistors, together with r10 and c3, also define the time constant of the comparator?s output filter. the impedance has to be quite high to reduce the c3 capacitor value. it is recommended to set the divider current to 10a, which means: 500k ? 10 0 5v r9 r8 = = + (19) figure 13. two-level boost output voltage implementation
AN-8021 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 6/1/10 9 the desired resistor values can be calculated based on the desired v out,l voltage level as: () r9 r8 v 5v v 3v r9 h out, l out, + ? ? ? = (20) where 3v is the nominal value of the error amplifier reference, 5v is the voltage at the 5vb pin, v out,h is the higher output voltage, v out,l is the lower output voltage level, and the sum of r8 and r9 is given by equation (19). assuming a total impedance of 500k ? , r8 is given by a subtraction: r9 500k ? r8 ? = (21) for most applications, r10=5k ? and c3=0.47f provide sufficient filtering and current limiting for the output of u2. the switch-over between the two output voltages occurs at a user-programmed input voltage level, v in,sw , determined by r11 and r12. following the method used in equation (19) through (21), assume a 50a divider; thus: 100k ? 50 0 5v r12 r11 = = + (22) () () r12 r11 r r 5v r v 2 r12 in2 in1 in2 sw in, + ? + ? ? ? = (23) r12 100k ? r11 ? = (24) the recommended hysteresis window is half of the comparator?s trip threshold and it can be programmed by r13 according to: r12 r11 r12 r11 r13 + ? = (25) the transistor q1 can be a small-signal nmos component, such as 2n7002 or similar device. its on-state impedance should be negligible compared to r13 resistance and it is chosen because its gate can be directly driven by the output of u2. even though u2 fulfills a comparator function, it can be an operational amplifier device. the wide hysteresis window set by r13 ensures that the output changes state only once per the period of the rectified ac input waveform and the minimum pulse width is at least one quarter of that time interval. therefore, an operational amplifier is able to switch reliably between states, allowing the user to implement u1 and u2 with a dual operational amplifier in a single package. boost follower implementation as opposed to two discrete output voltage levels, it is possible to design the pfc boost converter to continuously adjust the output as a function of the input voltage. this approach is known as the ?boost follower? method where the output voltage is a predetermined minimum voltage above the peak of the input ac voltage waveform. figure 14 shows a potential implementation of a boost follower using the fan9612. 3 r9 r14 error amplifier fan9612 8 7 6 comp ss fb c ss 5vb r15 r8 r6 r7 c1 c2 r in2 r in1 10 vin v in (t) d1 u1 u2 d2 v insns,ave r10 c3 figure 14. boost follower schematic diagram
AN-8021 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 6/1/10 10 the circuit utilizes the input voltage sense divider formed by r in1 and r in2 , which is already present in the design providing the scaled-down version of the input voltage for the vin pin. in addition, an averaging filter comprised of r6, r7, c1, and c2 is needed. this circuit is identical to the one introduced in figure 10. the minimum output voltage is set by r8, r9, r10, and c3. the circuit in figure 13 sets the lower output voltage in the two-level boost example. the interface between these two circuit blocks is provided by the gain stage comprised of u2, d2, r14, and r15. the gain stage scales the average input voltage measurement to the appropriate level to adjust the output voltage to the desired value. the ultimate reference voltage of the error amplifier is superimposed across the soft-start capacitor using the previously introduced concept of the ?sink-only, ideal diode? circuit composed of u1 and d1. similar to the earlier design examples, a few operating parameters must be selected before the component values can be calculated. these are the minimum output voltage level of the converter, v out,l , and the minimum reverse voltage across the inductor during the conduction interval of the boost rectifier diode, v l,min . for proper selection of these parameters, refer to the important considerations outlined in the two-level boost output voltage implementation section. the design procedure to set the minimum output voltage of the converter is identical to the steps of the two-level boost output voltage adjustment except the r8, r9 divider current is not critical and its current rating is increased to 50a for better noise immunity. note that the combination of r14 and r15 resistors is connected parallel to r9. to simplify the calculation, it is assumed that: r15 r14 r9 + = (26) thus the equivalent resistance of the r9, r14, r15 network becomes half of r9: 100k ? 50 0 5v 2 r9 r8 = = + (27) the desired resistor values can be calculated based on the desired v out,l voltage level as: 100k ? v 5v v 3v 2 2 r9 r8 v 5v v 3v 2 r9 nom out, l out, nom out, l out, ? ? ? ? = ? ? ? ? ? ? + ? ? ? ? = (28) where 3v is the nominal value of the error amplifier reference, 5v is the voltage at the 5vb pin, v out,nom is the nominal output voltage, v out,l is the lowest output voltage level, and the sum of r8 and half r9 is given by (27). assuming a total impedance of 100k ? , r8 is given by subtraction: 2 r9 100k ? r8 ? = (29) for most applications, r10=5k ? and c3=0.47f provide sufficient filtering and current limiting for the output of u2. the transfer function between the input rms voltage and the v insns,ave signal is given by: in2 in1 in2 rms in, ave insns, r r r v 2 2 v + ? ? ? = (30) the necessary gain is set by r14 and r15. for a non- inverting gain stage, the dc gain can be expressed as: r15 r14 r15 1 k gain + + = (31) furthermore, the gain can be determined at the critical input rms voltage when the sum of the peak line voltage and the minimum inductor reverse voltage equals the minimum output voltage level. this relationship is given by: () in2 in2 in1 min l, l out, nom out, l out, gain r r r v v v v 3v 2 k + ? ? ? ? ? = (32) after equating the right-side expressions of equations (31) and (32), substituting the relationship in equation (26), the result can be rearranged to: () () r9 1 r v v v 2 r r v 3v r15 in2 min l, l out, nom out, in2 in1 l out, ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? = (33) based on equation (26), the value of r14 is: r15 r9 r14 ? = (34) using this procedure, the boost follower design adjusts the output voltage of the power factor corrector according to the input rms voltage according to figure 15. v out 100v 200v 300v 400v v in,pk v in,rms 265v 65v figure 15. boost follower output characteristic as a function of the input rms voltage
AN-8021 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 6/1/10 11 v in,rms 265v 65v v l,min 50v 100v 150v figure 16. minimum reverse voltage of the boost inductor as a function of input rms voltage in addition, the implementation guarantees that the inductor has a minimum reverse voltage during the boost diode conduction time acco rding to the v l,min value chosen, as demonstrated in figure 16. the importance of the inductor?s minimum reverse voltage can be appreciated when the operating frequency of the bcm pfc converter is analyzed. during the conduction interval of the rectifier diode, the boost inductor current is decreasing at a rate proportional to the voltage across the inductor and its inductance. the converter?s output voltage has a notable impact on the di/dt and impacts the operating frequency of the power supply. in a bcm pfc design, the minimum operating frequency is the most important parameter to size the emi filter. the minimum frequency operation occurs at maximum load, minimum input rms voltage, and at the peak of the ac input voltage waveform. the conduction time of the boost transistor is proportional to the input voltage, output power, and the inductance of the boost choke. the conduction time of the boost diode is determined by the same parameters in addition to the output voltage. when the output voltage of the converter is reduced, the on-time of the boost switch does not change, but the diode conduction time is extended. figure 17. minimum operat ing frequency comparison of the boost follower and fixed output voltage pfc the operating frequency is lower. this phenomenon is shown graphically in figure 17 using a boost follower application that follows the output characteristic depicted in figure 15, compared to a fixed output voltage implementation. figure 17 exemplifies a specific design of a dual-phase, 440w pfc converter (220w per channel using fan9612) with a nominal output voltage of 400v and a 200h inductor in each power stage. it demonstrates the effect of the variable output of the follower implementation on the minimum operating frequency. the most important frequency values are listed in 0. this comparison highlights the fact that the boost follower?s operating frequency is lower in the entire input voltage range until the output reaches the nominal voltage level (400v, in this example). the boost follower produces approximately 20% lower absolute minimum frequency at the minimum input voltage (65v rms). the lower operating frequency is beneficial to reduce switching losses. in addition, when the converter operates at a reduced output voltage, the reliability of the power supply might improve due to the relaxed component stresses. on the other hand, lower frequency operation might increase the emi filter size and the lower output voltage requires larger output capacitance. table 2. frequency comparison of the boost follower and fixed output voltage pfc converters v in boost follower fixed output (v out =400v) f sw,min v out f sw,min 65v rms 30khz 240v 37khz 120v rms 48khz 240v 94khz 140v rms 39khz 240v 112khz 198v rms 65khz 328v 134khz 230v rms 88khz 381v 112khz 265v rms 50khz 400v 50khz
AN-8021 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 6/1/10 12 furthermore, the downstream dc-dc converter must be designed for a wide input voltage range that might negatively impact its efficiency and the selection of suitable topologies. lastly, it is interesting to look at the operating frequency characteristics of the bcm pfc when the output power has control over the boost output voltage. in this implementation, the decreasing output power pushes the operating frequency higher. at the same time, the output voltage is adjusted lower, which has an effect of lowering the switching frequency. the combination of these two opposing trends at light load still results in higher frequency operation than at full load, but the frequency increase is reduced. the lower frequency operation, coupled with the lower switching losses due to the lower output voltage, provides a measurable improvement in efficiency at light load. also, the output capacitor size remains relatively small and the hold-up time requirements are met under all operating conditions. additional implementation details the external circuits needed to implement the various output voltage adjustment schemes must work with the existing internal circuits of the fan9612. to achieve the desired accuracy of these solutions, the external circuits and their interface to the fan9612 must meet certain requirements. most of these requirements relate to the fan9612?s error amplifier. the typical error amplifier configured with its compensation network is shown in figure 18. figure 18. error amplifier with a compensation network the fan9612 employs a g m -type error amplifier. the output of this device is a current proportional to the voltage difference between its inverting and non-inverting inputs. usually, the compensation network has no dc path to gnd or any other circuit nodes, as shown in figure 18. therefore, during normal operation, the output current is zero and the feedback pin is equal to the amplifier?s reference voltage at the ss pin. the output voltage is regulated at the desired voltage as determined by the r fb1 and r fb2 resistors. when the error amplifier output is terminated with a resistive component, a dc current must flow, even during steady- state operation. this dc current requires a voltage differential between the inputs of the g m -type error amplifier. consequently, the inverting input is not equal to the non-inverting input and an output voltage regulation error occurs. this offset is proportional to the g m of the amplifier and the output current of the device. fb2 fb2 fb1 m comp offset out, r r r g i v + ? ? = (35) where i comp is a positive number when the current is sourced by the amplifier. when the output voltage is adjusted by the output power of the converter, the comp pin must be utilized. the schematic diagrams in figure 6, figure 8, and figure 10 are examples of such solutions. to minimize the output voltage offset, the resistive dividers connected to the comp pin in those circuits must be high impedances to limit the current fed into the error amplifier?s output. another high-impedance circuit node that requires attention is the non-inverting input of the error amplifier connected to the ss pin of the fan9612 controller. as shown in figure 18, the internal circuits tied to that pin are a small current source and a precision clamp circuit represented by the zener symbol. the current source is in the 5a range and the clamp is designed for high precision, but low current operation. the pin should be considered a high impedance node; therefore, external circuits could easily pull the ss pin above the nominal 3v level of the clamp circuit, causing the output voltage to rise above the nominal value. to eliminate the possibility of causing output over-voltage by pulling the ss pin above its nominal 3v level, all the output voltage adjustment circuits are interfaced to the ss pin using the ?sink-only ideal diode? circuit. the ideal diode circuit had been pictured in all schematics and is comprised of an operational amplifier and a small signal diode. depending on the orientation of the diode, the circuit implements a ?source-only? or a ?sink-only? diode function. it is considered id eal because the forward voltage drop is eliminated. using only a diode instead of the ideal circuit would be troublesome due to the inaccuracy and temperature dependency in the forward voltage drop of the pn junction. in most of the featured circuits, the error amplifier?s reference is adjusted only a few hundred millivolts, which is comparable to the temperature variation of the diode?s forward voltage drop. therefore, to achieve any reasonable accuracy, the ideal diode circuit is necessary. summary the trade-offs of variable output voltage for power factor correctors were analyzed. the fan9612 controller with varying complexity of external circuits was introduced to adjust v out . step-by-step design procedures were given.
AN-8021 application note ? 2009 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.1 ? 6/1/10 13 author biography laszlo balogh is a technical fellow and a system engineer at fairchild semiconductor. he received his msee degree from the technical university of budapest, hungary, in 1983. after working several years designing power supplies for space, telecom, and industrial applications; he joined unitrode, now texas instruments, in 1994. in 2005, laszlo joined fairchild semiconductor where he works in the high- power solutions team. laszlo is responsible for the development of various analog and digital pwm controllers, power supply support integrated circuits, and their application support. in his 26-year career in power management, laszlo has authored many conference papers and application notes, has numerous granted and pending patents, and participates in organizing and presenting the fairchild power supply design seminar worldwide. related resources datasheet fan9611 / fan9612 ? interleaved dual bcm, pfc controller application note an-6086 ? design consideration for interleaved boundary conduction mode pfc using fan9612 application note an-8018 ? evaluation board feb279 user guide , 400w evaluation board using fan9612 fairchild power seminar 2008-2009 paper ? understanding interleaved boundary conduction mode pfc converters disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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